Local acceptance (2026-10-20): segmented exact-source coverage, both current long tests, installed wheel and original Linux frozen gates pass. Native CI remains separate; new fanout frozen-runtime chains remain NOT_RUN. Release paused. See validation status.

Open-source power electronics CAE toolkit for power-stage design, LLC, PFC, FRA, digital control, C99 code generation and switching verification.

Power Stage Designer · LLC · DAB TPS · Totem-Pole PFC · Vienna / Two-Level PFC · SRF / DDSRF / DSOGI PLL · Multi-harmonic PR · Magnetics · FRA · C99 · ngspice · Web / MCP

Power Design Toolkit is an engineering-oriented power-electronics design and digital-control platform. It connects power-stage design, component/loss screening, multi-fidelity models, measured FRA data, exact discrete controller H(z), stability analysis, C99 code generation, firmware-correlated switching co-simulation and Agent/API access in one codebase.

v9.9.0 development source: Power Stage Designer, shared-waveform LLC/PFC analysis, integrated LLC resonant magnetics, source-backed CSC selection, corrected circuit drawings and session/export safeguards. Historical Linux application/wheel/frozen results remain bound to the exact sources in the validation report; they are not reused for newer changes. Native snapshot 320b3e3 passed Linux CI and actual macOS frozen self-test/package upload. Windows acceptance and the newer Guided/control fan-out qualification remain pending. Formal release is paused. The published v9.8.1 binary baseline predates these additions. See validation and source identities, current control-stage validation and Install and run.

Guided loop follow-up: The launcher’s 系统建模与设计 / Guided System Design connects LLC FM and TTPL PFC models to their actual expert loop workspaces. Recent audits corrected timing/hold wiring, continuous-transfer coefficient preservation, per-loop Nyquist limits, ADC headroom checks and phase-budget composition. Default TTPL outer-loop margins remain low; a plotted Bode curve is not hardware approval. Other Guided topology adapters remain disabled, and saved expert settings are authoritative rather than the historical wizard form. See exact scope and validation; current-source whole-suite and package requalification are pending.

Reproducible LLC Two-Stage GUI/CLI input examples include a nominal WARN candidate with explicit Apply/save/report steps and a physically rejected candidate that must remain unavailable for Apply. They preserve the 20% validity gate and distinguish nominal TD losses from the remaining FHA workpoints.

Control-workspace fan-out (development checkpoint): DAB now exposes forward TPS/SPS power-command loops, exact controller import, explicit candidate Apply, retained operating points and reproducible report/C99 delivery. Two-level PFC uses the same exact native/imported H(z) in its nonlinear runtime, lifted local model and exports. Vienna adds per-loop valid bands, source-bound candidates, sessions and reports; its ABC model remains distinct from dq. See the capability matrix and stage validation. Complete fixed-source qualification of this checkpoint is pending; detailed analog ADC parity and Vienna timing/energy-chain corrections remain open.

One toolkit connects power-stage design, magnetics, loss estimation, voltage/current waveforms, control-loop design, measured FRA, digital coefficients and C99 export.

Source and binary releases: This page describes its source checkout; unpublished additions are identified above. Check the corresponding Release notes for features included in a binary package. The latest additions provide software models and data-based validation; they do not establish hardware closed-loop or high-voltage validation. Power Stage Designer, DAB and three-phase additions primarily target desktop/Python use; new Web/MCP coverage is not implied. C99 exports provide controller/PLL reference functions without board-specific PWM/ADC drivers.

Latest engineering additions: Detailed notes, limitations and reproduction (Chinese) · Control validation · Independent magnetic-model test · Optimization comparison · Regression scope (Chinese)

Latest reliability audit: Fixed stale controller exports, out-of-order PFC results, DAB Cp linearization/discrete-model consistency, and LLC three-phase waveform rendering. Each workspace shows Author: 杨帅 / Yang Shuai, email and WeChat in the existing upper-right toolbar row. The launcher puts 功率级设计 / Power Stage Designer first, with direct Buck/Boost/Buck-Boost/full-bridge descriptions and all existing workspace entries retained. See the earlier UI audit and current PSD/shared-consumer validation.

The project is built around four rules:

1. One engineering model, multiple front ends. Desktop GUI, CLI, Web/API, MCP and code generation reuse shared Python kernels instead of re-implementing equations in each interface.
2. Exact digital-control semantics. A designed discrete transfer function is passed as its real b/a coefficients; it is not silently re-fit into a different PI/PID form or re-discretized inside downstream simulation.
3. Model boundaries are explicit. FHA, HB, switched time-domain, measured FRA, small-signal Bode, firmware runtime and ngspice answer different questions.
4. Evidence is not collapsed into one word. Software regression, simulator execution and hardware validation are separate evidence levels.

Completed LLC and TTPL PFC control analyses can be exported as standalone MATLAB .m / Python .py research scripts, with exact controller coefficients, sample times, explicit frequency-data boundaries and numerical self-checks. See Research model export.

Digital Control Tools also includes a parallel multi-harmonic quasi-PR page (1/3/5/7/9/11, branch/total Bode, float32 coefficients and C99 functions). PFC inductor results provide measured complex-impedance fitting and SPICE export. See Multi-harmonic PR and magnetics.

Actual development-source Qt capture at 1280×720, 100% scale: the first-level Power Stage Designer entry and every existing workspace are visible. This Linux/offscreen capture does not qualify native Windows/macOS display scaling.

flowchart TD
    A["Specification and measured data"] --> B["Power stage and component models"]
    A --> C["Measured FRA and de-embedding"]
    B --> D["Plant and digital controller"]
    C --> D
    D --> E["Bode, margins and sampled poles"]
    E --> F["Exact H(z) and C99"]
    E --> G["Closed-loop software verification"]
    G --> H["Optional switching correlation"]
    F --> I["Bench correlation and evidence"]
    H --> I

A typical LLC path is:

400 V -> 53 V / 3 kW specification
    -> Lr / Cr / Lm and operating region
    -> primary / SR device selection and comparison
    -> FHA / HB / switched-TD comparison
    -> digital voltage-loop model
    -> exact H(z) controller
    -> PM / GM / sensitivity checks
    -> C99 float32_t export
    -> shared-ngspice switching correlation
    -> traceable evidence matrix

A typical single-phase TTPL PFC path is:

Vin / Vbus / Pout / fsw specification
    -> Lboost / Cbus sizing
    -> MOSFET / loss / thermal screening
    -> settled AC line cycle / PF / THD
    -> switching / zero-crossing verification
    -> sensing / ADC / current + voltage loop design
    -> exact current + voltage H(z)
    -> C99 contract
    -> float32 sensing / ADC / delay / anti-windup / zero-cross runtime
    -> shared-ngspice four-switch closed loop
    -> hardware correlation

The first maintained reference case is LLC_400V_53V_3kW. Its bench status is intentionally UNKNOWN; software evidence is not presented as hardware sign-off.

The desktop launcher opens six independent workspaces while preserving state during switching, plus Guided System Design.

The PFC workspace includes a separate six-switch two-level dq plant with SRF/DDSRF/dual-SOGI PLL selection, decoupled current loops, voltage PI, SVPWM, and frequency/phase/load disturbances. The source angle is used only to generate the grid and evaluate error, never as controller feedback. Both three-phase topologies provide carrier-reconstructed stress/loss analysis and an independent PLL comparison experiment. See model contracts and the current expansion.

Click the first launcher card, 功率级设计 / Power Stage Designer → 进入功率级设计, or run python -m power_stage_design. Choose Buck, Boost, Buck-Boost or Full Bridge in the topology selector, edit the operating point, then click a physical schematic component to inspect its own voltage/current and stress statistics. On a short display, scroll the stage panel or collapse its schematic to view both plots and stress statistics together. The stage solver, component view, CSV and HTML report use the same calculated result.

• Direct stages: Buck, Boost, inverting Buck-Boost, Fly-Buck, two-switch Buck-Boost, SEPIC, ZETA, Ćuk, Flyback, two-switch Flyback, QR Flyback, active-clamp Forward, Forward, two-switch Forward, Half Bridge, Push-Pull, Full Bridge, phase-shifted Full Bridge and series-capacitor Buck. LLC Half Bridge and Full Bridge open the existing LLC engine with the selected bridge identity.
• Declared physical domains: Buck/Boost/Flyback support ideal periodic CCM/BCM/DCM with finite diode drop. Other stages retain their individual reset, load, ripple, commutation and conduction-mode restrictions; the topology name does not imply every operating mode. The ideal models remain available. An opt-in Advanced physical parameters tab adds explicit two-switch Coss/Ron/diode/winding dynamics, QR valley/delay/charge-curve and finite-Ron root policies, and a seven-state constant-Coss PSFB commutation model. Parameters, source and model revision are saved with each project. These are declared independent circuits/controllers, not inferred TI policies or hardware ZVS qualification. Their detailed bounds and acceptance evidence are in the feature matrix.
• Parameter suggestions: explicit ripple/duty/reflected-voltage targets produce L/Lm/turns-ratio proposals as applicable. Preview the achieved values, explicitly apply, and recompute. Saved provenance retains targets and achieved values. These are single-operating-point suggestions; scan corners separately. Half Bridge, Push-Pull and Full Bridge suggestions include ordinary and joint magnetic-state CCM/BCM/DCM branches, with achieved ripple and duty checked by the actual forward solver. PSFB also accepts an explicit Lm ripple target; untargeted Lm and physical options remain user supplied. The half-bridge split capacitors enforce a fixed total DC bus and a declared 10% individual-ripple limit. Advanced two-switch Buck-Boost/PSFB proposals preserve their explicit physical options through Apply, project restoration and reports.
• Analog loops: Buck VMC with Type II/III is the starting workflow. The complete calculator provides six strict-CCM plants: Buck VMC and peak-CMC Buck, Boost, inverting Buck-Boost, Forward and Flyback. Five physical compensation networks cover Type II, transconductance Type II, Type III, isolated Type II with Zener clamp, and isolated Type II with inner loop. An explicit exact integrator-branch action is available for the eligible networks, with the TI approximate-setting discrepancy explained. Ordinary edits refresh the current Bode analysis automatically. Target Fc/PM and preferred-series intent is saved separately from achieved results; synthesis reanalyzes the realized R/C values; finite amplifier, optocoupler and slope-compensation assumptions remain explicit. This analog analysis does not imply digital ADC/computation-delay qualification.
• Toolbox: FET loss screening, load-step capacitance, capacitor current sharing, AC/DC bulk and hold-up capacitance, RCD/RC snubbers, preferred-value dividers, analog/GPIO output scaling, unit conversion, and LC/π filters with damping. Toolbox parameters have their own JSON save/open and result exports, with page-local imported-source identity, debounced current-result refresh and cancellable heavy file-open recomputation. Desktop capacitor sharing is single-frequency; explicit harmonic spectra are a Python feature. The published bulk-capacitor RMS approximation is not thermal-validated periodic RMS.
• Corner scans: explicit Vin/load/component-tolerance combinations evaluate the same compensator, with per-metric worst-point identities. Unscanned regions and unknown total losses remain unverified.
• Reproducibility: project JSON preserves full-precision inputs, model/controller/device snapshots, suggestions and scan requests. Reopening validates and recomputes; saved hashes or historical results are not fresh evidence. Input changes, stale asynchronous results and modal export races invalidate obsolete output. Export the current waveform CSV or printable HTML report, including matching loop and corner results.

Related LLC/PFC/control fixes: LLC HB/FB component selection now links primary/SR devices, windings and tank/output components to the same waveform result, including Co ESR and the modeled series resistance. Full Bridge also exposes signed DC-bus current and bus voltage. The ideal Half Bridge model does not resolve the redundant midpoint sources individually, so that source current remains explicitly unavailable. Accepted periodic TD waveforms feed semiconductor, magnetic, capacitor and damping calculations only for the matching converged operating point. PFC can use one qualified signed switched line-cycle source for PF/THD, device/capacitor losses, thermal screening and exports; incomplete PWM coverage cannot silently become full-period thermal evidence. Selected-device/bank overlays remain separate from the simulated circuit and require an electrical rerun after component changes. LLC SPICE dead-time current paths and PFC signed-current feedback were also repaired. Exact H(z)/FRA sessions preserve leading-zero delays and full-precision coefficients; stale analysis/candidate/export results are rejected across the existing workspaces.

LLC two-stage optimization: the LLC workspace now has a bounded Stage-A FHA → Stage-B TD candidate page. Choose nominal-only or critical-point verification, inspect each candidate's exact source/loss scope, then explicitly Apply. Reopened candidate records are historical only until rerun. The CLI opt-in is llc-design optimize --config project.json --profile current --two-stage --verification-scope nominal --top-n 1 --max-candidates 1 --output new-run-directory. Two-stage output requires a new directory so rejected reruns cannot mix current metadata with old accepted reports. Rejected/UNKNOWN candidates produce evidence and a nonzero exit; they never fall back to an accepted FHA report. The existing command without --two-stage retains Stage-A behavior.

Controller export evidence: the LLC, Control Tools and FRA exact C99 paths release a usable header only after the actual host float32 compile/run check passes. FAIL or NOT_RUN headers are compile-blocked diagnostics with hash-bound evidence. PFC semantic firmware templates separately label configuration checks, numerical verification and hardware status. A host-gcc PASS does not qualify an MCU, ISR timing or a board.

Acceptance boundary: the register covers 33 top-level stage/tool items, 11 nested loop plant/network items and six enhancements, for 50 explicit IDs. Its 30 verified-in-scope and three partial top-level labels are bounded capability labels, not release or hardware certification. Two-switch Buck-Boost, QR Flyback and PSFB retain unverified exact TI executable policies. Separately, unsupported model domains include asymmetric bridge/reset behavior, nonlinear commutation and zero-load/burst extensions where their rows exclude them; missing device/thermal data remain unknown. The integrated repairs now pass complete local regression and actual wheel/Linux frozen checks on their documented source identity. The separate CI file-dialog test correction and native Windows/macOS packages still require qualification. Existing measured-FRA analysis remains available; these software results do not establish new bench correlation, thermal/EMI or hardware safety. See the per-priority topology scope.

See the feature matrix, validation report and development status for the supported domains, independent checks and remaining gates.

Actual Linux/offscreen Qt capture after opening and recomputing the included Buck + VMC loop project; the stage waveform tab is shown. This is not a native Windows/macOS package test.

Selecting Operating point automatically starts calculation when needed. Electrical waveforms can replay at a 100 ms frame interval, with pause and phase reset. This replays one computed steady-state period; it does not manufacture a transient simulation.

The Voltage Loop / TPS Optimization tab reuses LLC digital-controller coefficients and adds:

• PI or exact imported C(z) → forward power command → TPS or SPS → capacitor/load → Vout;
• local power-map linearization, matched discrete bus-energy update and sample delay, Bode and discrete poles;
• reference/load steps with nonlinear bus-energy integration and command limits;
• formula/grid/multi-start constrained-search comparison and PWM-count checks;
• explicit candidate Apply and fixed-controller operating-point scans;
• typed sessions with fresh-process replay, HTML/JSON reports, standalone research scripts and portable controller C99.

The input remains power command in watts: SPS phase is obtained by inversion. A raw phase-command controller and reverse-power loop are not implemented here. See DAB workflow and limits.

The optional Cp path is a periodic power map, not a complete Cp/L transient state-space model. The optimizer uses exact ideal-L segment integrals and does not claim global optimality or ZVS proof.

The FRA toolbar also opens a measured PI tuning map: bind each scan to its actual controller and operating point, compare rounds on a sparse Kp×Ti map, and plan a local next scan. Predictions remain separate from measurements; no hardware parameters are applied.

From the launcher, Guided System Design builds a canonical closed-loop definition for LLC FM voltage-loop or single-phase Totem-Pole PFC (current + bus voltage), then hands it into the existing design/control engines. An interactive Fc–PM Solution Map synthesizes Tustin PI candidates for explicit application in the LLC/TTPL workspaces.

The eight-step workflow is Topology → Power Stage → Sensing → ADC → Modulator → Timing → Controller → Review, with live summaries and guided-definition re-entry. LLC envelope/ZVS/FHA–TD/loss-provenance/thermal/optimizer foundations are described in LLC Physics Model V2.

v9.8.1 makes the assessment and its limits explicit:

• Actual LLC output headroom: static normalized-PCMD headroom uses the active PI/PIF/2P2Z controller's output_min/output_max, intersected with the FM LUT's reachable PCMD range and the actual 0–1 clamp. For example, PCMD 0.75 with an upper limit of 0.6 gives −0.15 upper headroom and a saturation warning. External H(z) without an absolute output-limit contract remains UNKNOWN; this is not a transient anti-windup test.
• Conditional adoption: FEASIBLE means configured checks pass within the analyzed frequency band. Missing Fsw attenuation or required phase-crossover/GM evidence can produce CONDITIONAL. Review the reasons, enable Allow conditional PI (unverified Fsw / GM), then explicitly Apply conditional PI. This does not upgrade missing evidence to a pass; UNKNOWN candidates and known constraint failures still block Apply.
• One PI across retained points: analyze a real operating point, click Retain current, then repeat and select compatible snapshots. The nominal PI is evaluated unchanged at every selected point, with per-point results and worst observed metrics. Uncollected load/voltage/temperature/tolerance conditions remain unverified; missing pole-stability evidence remains UNKNOWN.
• Traceable exports: Apply preserves conditional reasons, constraints, per-point results, exact controller identity and model/response signatures in LLC project JSON, MATLAB/Python research metadata, LLC/TTPL C99 design snapshots and TTPL H(z) manifests. Changed inputs, models, controllers or selected points invalidate stale candidates/evidence.

LLC Save project JSON includes the control session; the PFC toolbar provides Save / Open TTPL session. Sessions preserve full-precision controller and model inputs, hidden sampling/sensing/timing fields, retained points, constraints and historical candidate/applied evidence. Legacy LLC spec/project files remain readable. This covers LLC/TTPL control design, not every workspace or FRA measurement session.

Reopening restores inputs and history only. Saved curves, hashes and PASS/CONDITIONAL assessments are not fresh validation: Apply is disabled and conditional permission is reset. Run the model again → regenerate candidates → explicitly Apply. A selected point that cannot be recomputed blocks candidate generation until it is successfully rebuilt or explicitly deselected/removed. Files are validated before changing the current session and saved atomically.

See Smart Control evidence, common operating points and sessions (Chinese). These changes add software/model evidence, not hardware measurements, real ISR timing qualification or new float32 validation.

The measured FRA PI experiment map and MATLAB/Python research exports remain available. Measured scans and local predictions stay separate; rational models and frequency-response data retain their declared boundaries. Python research scripts are regression-tested; MATLAB runtime execution has not been validated.

Roadmap placeholders for other topologies are shown explicitly — they are not silently claimed as supported. Solution Map synthesis currently targets Tustin PI. Some advanced physics paths remain API/opt-in and are not yet integrated into every default GUI/PDF/Web consumer; see the explicit model limitations.

The LLC workspace keeps several model levels instead of forcing one solver to do every job:

• FHA — fast fundamental-harmonic design baseline for tank synthesis, gain and operating-point work.
• Nonlinear multi-harmonic HB — selected odd harmonics with rectifier commutation/polarity coupling.
• Internal switched time-domain solver — piecewise nonlinear switching model with periodic steady-state solution.
• shared-ngspice verification — optional circuit-level switching correlation driven by the toolkit's discrete controller runtime.

The analysis also includes multi-load Q/gain maps, theoretical and engineering ZVS regions, operating trajectories, waveform reconstruction, transformer/resonant-inductor design, synchronous-rectifier timing/loss analysis, and fixed 2-phase/3-phase interleaved LLC analysis.

The LLC workspace includes built-in engineering-reference MOSFET records for primary and synchronous-rectifier positions, plus a persistent user library.

Current device-library workflow includes:

• Primary MOSFET and SR MOSFET selection;
• create / edit / clone / delete user records;
• JSON import/export;
• built-in reference data kept separate from user data;
• device comparison using the current LLC operating point;
• conduction, turn-off, gate, Coss/deadtime and ZVS-margin related screening where the model provides the required data. Built-in generic/reference devices are not presented as vendor hardware sign-off. Datasheet curves and traceable vendor provenance remain a higher-fidelity data layer.

Vref
 -> C(z)
 -> PCMD clamp
 -> PCMD/Frequency or PCMD/TBPRD FM block
 -> PWM / ZOH / timing delay
 -> Gvf
 -> Vout
 -> analog sensing
 -> ADC / multi-SOC / recursive averaging
 -> feedback

The analyzer reports detected gain/phase crossovers, phase/gain margins, sensitivity/complementary sensitivity, delay envelopes, discrete closed-loop poles, command headroom and polarity diagnostics.

Transformer design now provides search, shape filtering and parameter loading from 46 complete presets, including 44 source-traced TDK core/bobbin pairs. Another 137 legacy records remain searchable as reference data. Incomplete records and geometry conflicts are visible; core-window area is kept separate from usable bobbin winding area. Material fits and geometric/thermal assumptions retain their source pages, rows and warnings.

The catalog also opens measured sinusoidal core-loss CSV comparison and an optional bounded 3C90 waveform predictor. It never substitutes that predictor for PC40/PC44 or another material. See magnetic validation (Chinese).

The LLC global input panel offers 磁件结构 / 集成谐振漏感 alongside the separate-Lr default. Supply a declared two-winding inductance matrix or consistent open/short measurements to derive Lr, APR Lm and the effective electrical ratio together. Physical core flux, winding geometry and loss use the actual turns ratio; the shared transformer has no duplicate external-inductor loss or thermal node.

The winding screen includes insulation spacing, required build and unreachable leakage targets. Its labeled reference examples are software models, not tested hardware. Saved inputs, calculation books and formula PDFs retain source identity, the physical/APR distinction and geometry limits. See the integrated LLC workflow for input definitions and the two-winding/full-bridge-secondary scope. Five independent actual consumer/identity/boundary/projection/TD-label checks pass on application source 4f9f5b4; the installed wheel and actual Linux frozen runtime checks also pass. Native Windows/macOS qualification remains separate and pending.

The added CSC reference catalog preserves 630 printed part numbers, 318 source-specific geometry records, 1,294 availability rows and 44 printed bias/loss formulas from the supplied 2025 catalog. These counts are separate: a geometry or an availability row is not a manufactured SKU. Three companion documents remain separately searchable, including their application example and source conflicts. The original PDFs are not bundled as application assets.

Open PFC → TTPL Engineering / Vienna → 电感设计 → CSC PDF 来源磁环. Search a printed part, inspect its source pages and missing fields, and calculate zero-bias inductance or bounded native-unit formula references. 保存磁件工程, 打开磁件工程 and 磁件报告 preserve the selected source snapshot and recompute its outputs. The LLC transformer catalog also exposes these records as reference data; powder-core geometry does not become a complete ferrite/bobbin preset.

Full PFC reference estimation requires an explicit, saved user model declaration when the PDFs do not define the loss-flux convention, waveform or application range. Defaults remain UNKNOWN. Conflicting identities cannot be overridden by a generic declaration, and legacy High Flux coefficients are never silently used. The worked 120 kHz / 1 kW document is an arithmetic replay of its own assumptions, not a production-solver acceptance case or manufacturer/hardware qualification. Current source/consumer and final artifact acceptance are tracked in the validation report.

The current ngspice layer is a switching-correlation model, not a vendor semiconductor sign-off model. It does not claim release-accurate nonlinear Coss commutation, Qrr, switching loss, ringing or SR device stress.

See ngspice closed-loop architecture.

The TTPL path is organized as an explicit eight-stage engineering workflow:

1. Power Stage / Sizing
        ↓
2. Devices / Loss
        ↓
3. Capacitor / Thermal
        ↓
4. AC Line / PF / THD
        ↓
5. Switching / Zero Crossing
        ↓
6. Control / Sensing / Bode
        ↓
7. Exact H(z) / C99
        ↓
8. Closed-Loop Verification

The deterministic engineering kernel covers specification-to-hardware calculations including:

• low-line input RMS/peak current;
• duty trajectory over the AC half-cycle;
• boost-inductor ripple scan and required Lboost;
• twice-line bus-ripple capacitance requirement;
• hold-up capacitance requirement;
• physical capacitor-bank selection and ESR transfer into downstream models.

TTPL device screening includes HF active/synchronous positions and the line-frequency leg. The device database supports packaged records plus persistent user JSON records. Loss/thermal calculations remain engineering screening models; nonlinear vendor Coss/Qrr/Eon/Eoff surfaces and detailed heatsink/airflow correlation are separate fidelity layers.

The time-domain PFC path provides:

• settled AC-line-cycle reconstruction;
• signed grid current versus rectified inductor current semantics;
• PF, displacement/distortion factor and integer-harmonic THD;
• DC-bus ripple and capacitor RMS current;
• selected-workpoint switching waveforms;
• minimum-pulse and zero-crossing state-machine observability.

The analyzed current and voltage controllers are promoted into a formal PFCControlHandoff containing exact normalized b[], a[], sample rates, limits, provenance and nonlinear implementation semantics.

H(z) = (b0 + b1 z^-1 + ...)/(1 + a1 z^-1 + ...)
y[n] = sum(b[k] x[n-k]) - sum(a[k] y[n-k])

Downstream PFC simulation consumes those coefficients directly. No Kp/Ti reconstruction and no second S-to-Z conversion are allowed in the closed-loop handoff.

The Exact H(z) stage can export the JSON contract and an audited C99 package.

The TTPL closed-loop verifier now connects the frozen H(z) controllers to a four-switch shared-ngspice power stage. The current fidelity layer includes:

• float32 controller/state execution;
• PI/PIF conditional-integrator anti-windup derived from the frozen discrete controller identity;
• 2P2Z clamped-output history semantics;
• configured analog sensing poles;
• ADC-resolution quantization in calibrated engineering units;
• multi-SOC recursive averaging and digital filtering;
• configured control/computation/PWM timing;
• PWM shadow-application timing;
• eight-state TTPL zero-crossing runtime with PI reset and commutation states;
• line-polarity-aware HF/LF gate scheduling;
• real libngspice continuous inductor/capacitor state between digital events.

This is firmware-correlated switching co-simulation, not a claim of instruction-level C2000 bit identity. The current schema does not yet encode board-specific ADC common-mode offset/rail clipping, full MCU peripheral register behavior, vendor nonlinear semiconductor models, layout parasitics or protection-state-machine hardware correlation.

See PFC Engineering Workspace, Exact H(z) handoff and ngspice closed-loop architecture.

Vienna currently includes:

• DC-voltage outer loop plus stationary-frame ABC current loops;
• split-bus midpoint balance loop;
• three-phase voltage/current and split-bus sensing;
• common-mode / third-harmonic modulation support;
• full three-phase line-cycle solution and sector analysis;
• three-level switching waveforms;
• per-phase PF/THD and power analysis.

New three-phase analysis adds inductor/device RMS and peak currents, switch and capacitor-current waveforms, copper/core/device/capacitor loss breakdowns, and PF/ITHD reporting. Vienna distinguishes back-to-back MOSFET and **diode bridge

• single MOSFET** center-switch implementations. Missing loss inputs are listed; reported efficiency includes only configured loss terms.

The Vienna voltage plant now includes inductor-energy dynamics, the boost RHP zero, copper loss and R/CPL load slope. Existing current/voltage/midpoint Bode, sensing and delay models remain topology-specific. Carrier reconstruction is a local CCM screening model; zero-crossing DCM, device parasitics and hardware correlation remain outside its scope. Circuit-level Vienna closed-loop coverage does not follow from TTPL ngspice support. The present line-cycle waveform does not apply every Bode delay and does not yet share the complete bus-energy loss chain; changing those frequency-domain settings is not a matching transient validation. See Vienna workflow and explicit model gaps.

The two-level model provides abc RL and bus-energy dynamics, measured-voltage PLL, dq current decoupling, voltage PI, current limits/slew and SVPWM. Its control page includes Gi(s)=1/(Ls+R), the current-to-bus energy plant, PWM delay and a lifted multi-rate voltage-loop model with margins and discrete-pole checks. The current native PI retains forward-Euler integration and the outer native PI retains backward-Euler integration, matching the time-domain runtime. Exact imported controllers, sampled sensing, Apply, retained corners and saved/exported source identity share this model. See the complete dq workflow contract.

The shared PLL experiment compares SRF / DDSRF / DDSOGI under the same frequency/phase step, negative sequence, voltage harmonics and sag. DDSOGI here means dual-SOGI positive-sequence DSOGI-PLL, not an MSOGI harmonic bank. Outputs include abc voltage, estimated phase, phase/frequency error, lock flags, positive-sequence alpha/beta, block diagrams and portable C99 implementations. Host-C agreement is checked; no TI-target timing or hardware validation is claimed.

power_control_tools is the common controller/filter engine used across the project.

Current structures include:

Integrator · PI · PIF · PID · PIDF · Type-II · Type-III · Modified PI · Lead · Lag · 1P1Z · 2P2Z · 3P3Z · General · Parallel Multi-harmonic Quasi-PR

Supported workflows include:

• analog controller/filter definition;
• Tustin, prewarped Tustin and backward-Euler discretization;
• exact discrete frequency response;
• Bode, step/impulse and pole-zero analysis;
• DF2T/SOS coefficient representation;
• single-file C99 float32_t export;
• generated-C verification against the Python reference when a C compiler is available.

Select any subset of harmonics, configure each branch's Kr and bandwidth, and add the common Kp once. Inspect branch/combined analog, digital and float32 Bode curves, exact coefficients, output limits and C99 functions. The export includes coefficient update, IIR section, initialization, reset and controller step functions corresponding to the supplied control-function convention.

This is a parallel resonant bank, not a cascade of resonant sections. Controller Bode alone does not prove power-stage closed-loop stability. See equations, coefficient signs and C integration.

Canonical coefficient convention:

H(z) = (b0 + b1 z^-1 + ...)/(1 + a1 z^-1 + ...)

y[k] = Sum(bi*x[k-i]) - Sum(aj*y[k-j])

See Digital control architecture.

The FRA workspace is the measured-frequency-response path for controller redesign and verification.

• Bode100 CSV
• SIMPLIS TXT (frequency / gain / phase)
• Generic frequency/gain/phase text or CSV

The GUI does not infer physical meaning merely from file columns. The user explicitly selects whether the measurement is:

• Plant TS — already the plant/equivalent response; or
• Complete Loop TS — includes the existing controller and requires de-embedding.

For a measured complete loop:

L_meas(jw) = C_old(jw) * G_rest(jw)
G_rest(jw) = L_meas(jw) / C_old(jw)
L_new(jw)  = C_new(jw) * G_rest(jw)

Raw measured complex points remain the authority for crossover and stability metrics. Low-order rational identification is optional and does not overwrite the measurement.

See FRA Loop Designer engineering contract.

Power Design Toolkit distinguishes software reproducibility, model correlation and hardware validation.

The common rule is:

analytical model
 -> higher-fidelity software model
 -> firmware-correlated runtime
 -> circuit simulation
 -> measured hardware
 -> reviewed release evidence

Passing an earlier stage is evidence, not permission to skip a later stage.

Historical complete local qualification on 6138f0fd36f07539f78ed208ca4cdee5ce2f136d (tree-identical to remote 02c2ca3) recorded 4,512 passed, 2 opt-in skips and 2 historical expected failures, followed by both long consumers. Later installed-wheel/frozen results remain bound to their documented sources. Native snapshot 320b3e3 subsequently passed Linux CI and macOS full-suite, actual frozen self-test and package upload; Windows remained pending at this checkpoint. These results do not qualify the newer Guided/control fan-out. Its predecessor full run stopped at 66% without a terminal result and is INCOMPLETE; a new exact-source full/wheel/frozen qualification is required. See current control-stage evidence and retained historical validation. Publication remains paused; none of these software checks qualifies hardware or expands model domains.

The historical application regression on clean source 4f9f5b4513a62fa9c5effb1b4cad5beacf36daac completed: 4,140 passed, 2 opt-in skips, 2 historical expected failures and 43 warnings in 2,728.51 s, exit 0, with all 760 tracked-file hashes unchanged. Final native owner/scene/plot/menu/group counts were zero; peak aggregate RSS was 1,847,560 KiB. The skips are the long real-PFC GUI and finite-Coss PSFB joint-sizing cases; both separate reruns passed on the same exact application source, and the installed-wheel/Linux frozen runtime checks passed on 759a8fb54a0443a2e97125335dc69b61b5942ec7. The expected failures retain the backend single-2P2Z attainable-phase-margin limit. The final artifact/push SHA and any CI/docs-only source difference must be recorded separately; this full result must not be relabeled as a run on a later SHA. Earlier bfc8bd9 results remain historical. See PSD validation.

Actual bench measurements are still needed to diagnose application-specific material, waveform or missing-loss errors. Reproduction scripts, data hashes, training/test boundaries and limitations are in the engineering expansion.

Start with:

• Engineering validation policy
• Reference Designs
• Project JSON / provenance contract
• Engineering device/magnetics data policy

v9.9.0 is pending native package verification and publication. The links below are intended release assets, not a claim that downloads are already available. Use the source instructions for the new features, or the published v9.8.1 release for the earlier binary baseline. Once published, choose the platform ZIP under Assets, not GitHub's source-code archives. Python is not required for binary packages.

The planned release assets also include SHA256SUMS.txt and frozen-app self-test reports for Windows and macOS. Unsigned macOS builds may require approval through Finder Open after verifying the source. CI gates are described in Release process; they establish software startup/resource evidence, not hardware sign-off. Optional shared-ngspice verification still requires a separate libngspice installation.

• Python 3.10+
• Windows / macOS / Linux
• PySide6 only for the desktop GUI
• ngspice/libngspice only for the optional SPICE path

Run source-install commands from the repository root:

git clone https://github.com/yangshuai2022-star/power-design-toolkit.git
cd power-design-toolkit
python -m pip install -e .

python -m pip install -e ".[gui]"
power-design-gui

The repository-root launchers LLC工具.bat (Windows) and LLC工具.command (macOS) start the same desktop application and can install missing GUI dependencies. These are Python/source launchers, not the packaged executables above.

Equivalent source-tree entry:

python -m llc_design gui

After the desktop installation above, launch directly:

python -m power_stage_design

Open the included Buck + VMC loop example, or recompute its HTML report directly:

python -m power_stage_design examples/power_stage_design/buck-loop.json
python -m power_stage_design examples/power_stage_design/buck-loop.json --report buck-loop-report.html

You can substitute a project saved from the workspace. The installed power-stage-design command accepts the same arguments. --report requires a saved project and runs without Qt, so the core installation is sufficient for headless report recomputation. This uses PSD project JSON, not an LLC or TTPL session file.

python -m pip install -e ".[web]"
power-design-web

Then open http://127.0.0.1:8000.

python -m pip install -e ".[agent]"
power-design-mcp

The MCP server uses the official Python SDK v2 and defaults to local stdio. See Agent / MCP interface.

python -m pip install -e ".[dev,gui,web,agent,research]"
pytest

On headless Linux, run GUI regression with QT_QPA_PLATFORM=offscreen python -m pytest. Optional live SPICE checks also need ngspice/libngspice; an offscreen run does not qualify a native desktop installer.

python -m pip install -e ".[research]"
python tools/benchmark_magnetic_physics.py
OPENBLAS_NUM_THREADS=1 python tools/benchmark_controls.py
OPENBLAS_NUM_THREADS=1 python tools/benchmark_dab_optimization.py

Re-training the optional 3C90 model requires the separately sourced reference data; original user PDFs/XLS and third-party datasets are not bundled. Ordinary application inference does not require scikit-learn. See sources and reproduction (Chinese).

llc-design
pfc-design
pfc-control-lab
vienna-control-lab
power-control-tools
power-control-codegen
power-design-gui
power-stage-design
power-design-web
power-design-mcp

The Agent layer follows one rule:

LLM for requirement interpretation and orchestration; deterministic kernels for engineering computation.

Initial MCP tools expose LLC defaults/analysis, toolkit capabilities and engineering-data provenance. Agent results explicitly retain their software-model scope and keep verified_for_hardware=false unless separate evidence proves otherwise.

ChatGPT / Claude / Codex / MCP host
               |
               v
        Power Design MCP
               |
               v
      deterministic kernels
        /       |       \
      LLC      PFC    Control/FRA

The browser UI does not duplicate engineering equations. FastAPI calls the same Python kernels used by desktop/CLI paths.

Current LLC endpoints include:

GET  /api/health
GET  /api/llc/defaults
POST /api/llc/analyze
GET  /api/llc/cores
POST /api/llc/optimize
POST /api/llc/report
POST /api/llc/report.xlsx
GET  /docs

Control API routes are mounted from backend.api.control into the same application.

See Web deployment.

Two CI layers are especially important:

• build-release — regression suite, package/version contract, real packaged-app --self-test, release artifacts;
• ngspice-smoke — installs real ngspice + libngspice and exercises switching integration rather than mocking the simulator.

The ngspice smoke suite now covers both LLC and TTPL integration paths. The packaged-app self-test constructs Qt workspaces offscreen and validates bundled data provenance. A release no longer passes merely because a PyInstaller directory exists.

The supported publish path is version bump on main → CI creates vX.Y.Z → packaging → GitHub Release. Do not hand-tag a mismatched version.

Full checklist and recovery steps: docs/RELEASE.md.

A reproducible real launcher screenshot can be generated with:

python scripts/capture_readme_screenshot.py docs/assets/power-design-toolkit-overview.png --language en

CI also produces the same screenshot as an artifact; the README should only embed a real captured UI image, never a mock.

power_stage_design/    Periodic power stages, schematics, analog loops, toolbox, projects/reports
dab_design/            DAB TPS, constrained optimization, sampled voltage control and GUI
llc_design/            LLC engineering, magnetics catalog/validation, control, GUI, reports
pfc_design/            TTPL/Vienna/two-level dq, PLLs, stress/loss, control and GUI
power_control_tools/   Generic controller/filter/FRA engine
power_codegen/         Portable C99 float32_t control-code generation
power_sim/             Backend-neutral digital runtime + LLC/PFC SPICE integration
power_agent/           Deterministic Agent wrappers + MCP v2 server
backend/               Shared backend/control API services
webapp/                FastAPI application + browser front end
reference_designs/     Traceable cases + evidence matrices
engineering_data/      Cross-workspace data catalog
schemas/               Shared project/provenance schemas
release_validation/    Version-controlled numerical regression baselines
tools/                 Reproducible catalog, magnetic/AI and control benchmarks
docs/                  Maintained engineering documentation and benchmark evidence
.github/workflows/      CI, release and real-ngspice validation

Start here instead of reading historical version notes:

• Documentation index
• Power Stage Designer feature matrix
• Power Stage Designer validation report
• Power Stage Designer development status
• Magnetics, DAB, PLL and three-phase expansion
• DAB / two-level dq conventions
• Multi-harmonic quasi-PR and magnetic modeling
• Digital control architecture
• Smart Control evidence, common operating points and saved sessions (Chinese)
• LLC model hierarchy and boundaries
• PFC Engineering Workspace
• PFC Exact H(z) handoff
• FRA Loop Designer engineering contract
• ngspice closed-loop architecture
• Engineering validation policy
• Project provenance
• Engineering data policy
• Agent / MCP
• Web deployment
• Release process
• Changelog

The application also contains an offline Help / F1 system in the workspaces, including implementation notes, model boundaries and known limitations.

The existing LLC/PFC/control/FRA desktop UI/help supports:

• English
• Simplified Chinese
• Japanese
• Korean

The new Power Stage Designer forms currently use primarily Simplified Chinese with stable English topology/tool identifiers; complete translation coverage is not yet claimed.

Engineering identifiers such as Bode, H(z), C99, Kp, PM, GM, FRA and component/model names intentionally remain stable across languages.

Author: 杨帅 (Yang Shuai)

Power Electronics · Digital Power · Embedded Control · Control Algorithms

• GitHub: yangshuai2022-star
• Email: [email protected]
• WeChat: maileyang
• Technical blog / WeChat official account: Switching Power Supply Simulation & Practical Design (Chinese account name: 开关电源仿真与实用设计)

For bug reports, include the toolkit version, topology/workspace, input parameters, expected result, actual result and relevant screenshot/export whenever possible.

GNU GPL v3.0 — see LICENSE.